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rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD13465 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 dual channel, 14-bit, 65 msps a/d converter with analog input signal conditioning functional block diagram 100 output terminators timing 3 11 14 14 enc enc d9a d10a d11a d0b ( lsb) d1b d3b d2b d4b d5b d6b d9b d10b timing d11b 9 5 enc enc b?n d12b d13b (msb) (lsb) d0a d1a d2a d3a d4a d5a d6a d7a d8a AD13465 drouta 100 output terminators amp-in-b-2 amp-in-b-1 amp-in-a-2 amp-in-a-1 amp-out-a a?n a+in b+in amp-out-b droutb drout vref d13a (msb) d12a d8b d7b vref drout features dual, 65 msps minimum sample rate channel-to-channel matching, 1% gain error 90 db channel-to-channel isolation dc-coupled signal conditioning 85 db spurious-free dynamic range selectable bipolar inputs ( 1 v and 0.5 v ranges) integral two-pole low-pass nyquist filter twos complement output format 3.3 v compatible outputs 1.8 w per channel industrial and military grade applications radar processing optimized for i/q baseband operation phased array receivers multichannel, multimode receivers gps antijamming receivers communications receivers product description t he a d13465 is a complete dual channel signal processing solut ion including on-board amplifiers, references, adcs, and output termination components to provide optimized system performance. the AD13465 has on-chip track-and-hold circuitry and utilizes an innovative multipass architecture to achieve 14-bit, 65 msps performance. the AD13465 uses state-of-the-art, high density circuit design and laser-trimmed t hin-film resistor networks to achieve exceptional channel matching and impedance control, and provide for significant board area savings. multiple options are provided for driving the analog input, including single-ended, differential, and optional series filtering. the AD13465 also offers the user a choice of analog input signal ranges to further minimize additional external signal condition ing, while remaining general-purpose. the AD13465 operates with 5.0 v for the analog signal conditioning, 5.0 v supply for the analog-to-digital conversion, and 3.3 v digital supply for the output stage. each channel is completely independent, allowing operation with independent encode and analog inputs, while main taining minimal crosstalk and interference. t he AD13465 is packaged in a 68-lead ceramic gull wing package. manufacturing is done on analog devices?mil- 38534 qu alified manufacturers line (qml) and components are ava ilable up to c lass-h (?0 c to +85 c). the components are m anufactured using analog devices?high speed compl emen tary bipolar process (xfcb). product highlights 1. guaranteed sample rate of 65 msps. 2. input signal conditioning included; gain and impedance matching. 3. single-ended, differential, or off-module filter options. 4. fully tested/characterized full channel performance. 5. pin compatible with 12-bit ad13280 product family.
rev. a C2C AD13465?pecifications (av cc = 5 v; av ee = ? v; dv cc = 3.3 v applies to each adc with front end amplifier unless otherwise noted.) test mil AD13465az/bz parameter temp level sub-group min typ max unit resolution 14 bits dc accuracy no missing codes full iv 12 guaranteed offset error 25 ci 1 ?.2 0.2 +2.2 % fs full vi 2, 3 ?.2 1.0 +2.2 % fs offset error channel match full vi 1, 2, 3 ?.0 0.1 +1.0 % fs gain error 1 25 ci 1 ?.0 ?.0 +1.0 % fs full vi 2, 3 ?.0 2.0 +5.0 % fs gain error channel match 25 ci 1 ?.5 0.5 +1.5 % fs max vi 2 ?.0 1.0 +3.0 % fs min vi 3 ?.0 1.0 +5.0 % fs single-ended analog input input voltage range amp-in-x-1 full v 0.5 v amp-in-x-2 full v 1.0 v input resistance amp-in-x-1 full iv 12 99 100 101 ? amp-in-x-2 full iv 12 198 200 202 ? input capacitance 2 4.0 7.0 pf analog input bandwidth 3 full v 100 mhz differential analog input analog signal input range a+in to a?n and b+in to b?n 4 full v 1.0 v input impedance full v 618 ? analog input bandwidth 3 full v 50 mhz encode input (enc, enc) 5 differential input voltage full iv 12 0.4 v p-p differential input resistance 25 cv 10 k ? differential input capacitance 25 cv 2.5 pf switching performance maximum conversion rate 6 full vi 4, 5, 6 65 msps minimum conversion rate 6 full iv 12 20 msps aperture delay (t a )25 cv 1.5 ns aperture delay matching 25 civ 12 250 500 ps aperture uncertainty (jitter) 25 cv 0.3 ps rms encode pulse with high 25 civ 12 5.0 7.7 9.5 ns encode pulse with low 25 civ 12 5.0 7.7 9.5 ns output delay (t od ) full iv 12 7.5 ns encode, rising to data ready, full v 11.5 ns rising delay snr 7 analog input @ 4.98 mhz 25 cv 72 dbfs analog input @ 9.9 mhz 25 ci 47 07 2 dbfs full ii 5, 6 69 71 dbfs analog input @ 21 mhz 25 ci 46 97 1 dbfs full ii 5, 6 68 70 dbfs analog input @ 32 mhz 25 cv 70 dbfs full v 69 dbfs sinad 8 analog input @ 4.98 mhz 25 cv 72 dbfs analog input @ 9.9 mhz 25 ci 46 97 2 dbfs full ii 5, 6 68.5 70.5 dbfs analog input @ 21 mhz 25 ci 4 65.5 70 dbfs full ii 5, 6 65 69 dbfs analog input @ 32 mhz 25 cv 63 dbfs full v 61 dbfs
rev. a C3C AD13465 test mil AD13465az/bz parameter temp level sub-group min typ max unit spurious-free dynamic range 9 analog input @ 4.98 mhz 25 cv 85 dbfs analog input @ 9.9 mhz 25 ci 48 08 6 dbfs full ii 5, 6 78 84 dbfs analog input @ 21 mhz 25 ci 46 97 6 dbfs full ii 5, 6 68 74 dbfs analog input @ 32 mhz 25 cv 63 dbfs full v 62 dbfs single-ended analog input pass-band ripple to 10 mhz 25 cv 0.05 db pass-band ripple to 25 mhz 25 cv 0.1 db differential analog input pass-band ripple to 10 mhz 25 cv 0.3 db pass-band ripple to 25 mhz 25 cv 0.82 db two-tone imd rejection 10 f in = 9.1 mhz and 10.1 mhz 25 ci 4 75.5 82 dbc f 1 and f 2 are ? db full ii 5, 6 74.5 80 f in = 19.1 mhz and 20.7 mhz 25 cv 72 dbc f 1 and f 2 are ? db channel-to-channel isolation 11 25 civ 12 90 db transient response 25 cv 15.3 ns digital outputs 12 logic compatibility cmos dv cc = 3.3 v logic 1 voltage full i 1, 2, 3 2.5 dvcc ?0.2 v logic 0 voltage full i 1, 2, 3 0.2 0.5 v dv cc = 5 v logic 1 voltage full v dvcc ?0.3 v logic 0 voltage full v 0.35 v output coding two? complement power supply av cc supply voltage 13 full vi 4.85 5.0 5.25 v i (av cc ) current full v 270 308 ma av ee supply voltage 13 full vi ?.25 ?.0 ?.75 v i (av ee ) current full v 38 49 ma dv cc supply voltage 13 full vi 3.135 3.3 3.465 v i (dv cc ) current full v 34 46 ma (total) supply current per channel full i 1, 2, 3 369 403 ma power dissipation (total) full i 1, 2, 3 3.57 3.9 w power supply rejection ratio (psrr) full v 0.02 %fsr/%v s notes 1 gain tests are performed on amp-in-x-1 input voltage range. 2 input capacitance spec. combines ad8037 capacitance and ceramic package capacitance. 3 full power bandwidth is the frequency at which the spectral power of the fundamental frequency (as determined by fft analysis) is reduced by 3 db. 4 for differential input: +in = 1 v p-p and ?n = 1 v p-p (signals are 180 out of phase). for single ended input: +in = 2 v p-p and ?n = gnd. 5 all ac specifications tested by driving encode and encode differentially. amp-in-x-1 = 1 v p-p, amp-in-x-2 = gnd. 6 minimum and maximum conversion rates allow for variation in encode duty cycle of 50% 5%. 7 analog input signal power at ? dbfs; signal-to-noise ratio (snr) is the ratio of signal level to total noise (first five harmo nics removed). encode = 65 msps. snr is reported in dbfs, related back to converter full scale. 8 analog input signal power at ? dbfs; signal-to-noise and distortion (sinad) is the ratio of signal level to total noise + harm onics. encode = 65 msps. sinad is reported in dbfs, related back to converter full scale. 9 analog input signal power at ? dbfs; sfdr is ratio of converter full scale to worst spur. 10 both input tones at ? dbfs; two-tone intermodulation distortion (imd) rejection is the ratio of either tone to the worst third order intermod product. 11 channel-to-channel isolation tested with a channel grounded and a full-scale signal applied to b channel. 12 digital output logic levels: dv cc = 3.3 v, c load = 10 pf. capacitive loads > 10 pf will degrade performance. 13 supply voltage recommended operating range. av cc may be varied from 4.85 v to 5.25 v. however, rated ac (harmonics) performance is valid only over the range av cc = 5.0 v to 5.25 v. specifications subject to change without notice.
rev. a AD13465 C4C absolute maximum ratings 1 electrical av cc voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 7 v av ee voltage . . . . . . . . . . . . . . . . . . . . . . . . . . ? v to 0 v dv cc voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v to 7 v analog input voltage . . . . . . . . . . . . . . . . . . . . . v ee to v cc analog input current . . . . . . . . . . . . . . ?0 ma to +10 ma digital input voltage (encode) . . . . . . . . . . . . . 0 to v cc encode, encode differential voltage . . . . . . . . . . 4 v digital output current . . . . . . . . . . . . ?0 ma to +10 ma environmental 2 operating temperature (case) . . . . . . . . . ?0 c to +85 c maximum junction temperature . . . . . . . . . . . . . . . 175 c lead temperature (soldering, 10 sec) . . . . . . . . . . . 300 c storage temperature range (ambient) . . ?5 c to +150 c notes 1 absolute maximum ratings are limiting values applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedance for ?s?package: jc , 2.2 c/w; ja , 24.3 c/w. test level i 100% production tested. ii 100% production tested at 25 c, and sample tested at specified temperatures. ac testing done on sample basis. iii sample tested only. iv parameter is guaranteed by design and characterization testing. v parameter is a typical value only. vi 100% production tested at temperature of 25 c; sample tested at temperature extremes. ordering guide model temperature range (case) package description package option AD13465az ?5 c to +85 c 68-lead ceramic leaded chip carrier es-68c AD13465af ?5 c to +85 c 68-lead ceramic leaded chip carrier es-68c with nonconductive tie-bar 5962-0150601hxa ?0 c to +85 c 68-lead ceramic leaded chip carrier es-68c AD13465/pcb 25 ce valuation board with AD13465az caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD13465 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. a AD13465 C5C pin function descriptions pin number mnemonic function 1, 35 shield internal ground shield between channels 2, 3, 9, 10, 13, 16 agnda a channel analog ground. a and b grounds should be connected as close to the device as possible. 4 a?n inverting differential input (gain = 1) 5 a+in noninverting differential input (gain = 1) 6 amp-out-a single-ended amplifier output (gain = 2) 7 amp-in-a-1 analog input for a side adc (nominally 0.5 v) 8 amp-in-a-2 analog input for a side adc (nominally 1.0 v) 11 av ee aa channel analog negative supply voltage (nominally ?.0 v or ?.2 v) 12 av cc aa channel analog positive supply voltage (nominally 5.0 v) 14 enca complement of encode; differential input 15 enca encode input; conversion initiated on rising edge 17 dv cc aa channel digital positive supply voltage (nominally 5.0 v/3.3 v) 18?5, 28?3 d0a?13a digital outputs for adc a. d0 (lsb) 26, 27 dgnda a channel digital ground 34 drouta data ready a output 36 droutb data ready b output 37?2, 45?2 d0b?13b digital outputs for adc b. d0 (lsb) 43, 44 dgndb b channel digital ground 53 dv cc bb channel digital positive supply voltage (nominally 5.0 v/3.3 v) 54, 57, 60, 61, 67, 68 agndb b channel analog ground 55 encb encode input; conversion initiated on rising edge 56 encb complement of encode; differential input 58 av cc bb channel analog positive supply voltage (nominally 5.0 v) 59 av ee bb channel analog negative supply voltage (nominally ?.0 v or ?.2 v) 62 amp-in-b-2 analog input for b side adc (nominally 1.0 v) 63 amp-in-b-1 analog input for b side adc (nominally 0.5 v) 64 amp-out-b single-ended amplifier output (gain = 2) 65 b+in noninverting differential input (gain = 1) 66 b?n inverting differential input (gain = 1) pin configuration 10 11 12 13 14 15 16 17 18 19 20 22 23 24 25 26 21 27 43 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 961 8765 68676665646362 4321 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 pin 1 identifier top view (not to scale) AD13465 agndb agndb d12a droutb agnda d0a(lsb) d3a d4a d5a d6a d7a agndb encb encb d0b(lsb) agnda agnda amp-out-a a+in a?n agnda amp-in-a-2 amp-in-a-1 agndb shield d3b d4b d5b dgnda d13b(msb) d12b d11b dgndb agndb b?n b+in agndb amp-in-b-2 amp-out-b amp-in-b-1 d10b d9b d8b d7b d6b dgndb shield drouta d13a(msb) d10a d11a d9a d8a dgnda enca enca agnda agnda d1b d2b d1a d2a av ee a av cc a dv cc a av ee b av cc b dv cc b
rev. a AD13465 C6C ?ypical performance characteristics 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 5mhz(?dbfs) snr = 72.12dbfs sfdr = 86.05dbc db tpc 1. single tone @ 5 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 21mhz(?dbfs) snr = 71.74dbfs sfdr = 73.07dbc db tpc 2. single tone @ 21 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 9.1mhz and 10.1mhz(?dbfs) sfdr = 85.01dbc db tpc 3. two-tone @ 9.1 mhz/10.1 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 9.9mhz(?dbfs) snr = 72.09dbfs sfdr = 84.04dbc db tpc 4. single tone @ 9.9 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 32mhz(?dbfs) snr = 70.8dbfs sfdr = 62.57dbc db tpc 5. single tone @ 32 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 65msps a in = 19mhz and 20.7mhz(?dbfs) snr = 70.8dbfs sfdr = 75.40dbc db tpc 6. two-tone @ 19 mhz/20.7 mhz
rev. a AD13465 C7C 3.0 2.5 2.0 1.5 1.0 0.5 0 ?.5 ?.0 0 14336 12288 10240 8192 6144 4096 2048 encode = 65msps dnl max = +0.632 codes dnl min = ?.52 codes 16384 lsb tpc 7. differential nonlinearity 0 ? ? ? ? ? ? ? ? ? ?0 1.0 3.5 6.0 8.5 11.0 13.5 16.0 18.5 21.0 23.5 26.0 frequency ?mhz dbfs encode = 65msps ro lloff = ?.18db tpc 8. pass-band ripple to 25 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 40msps a in = 9.1mhz and 10.1mhz(?dbfs) sfdr = 84.16dbc db tpc 9. two-tone @ 9.1 mhz/10.1 mhz 3.0 2.0 1.0 0 ?.0 ?.0 ?.0 0 14336 12288 10240 8192 6144 4096 2048 encode = 65msps inl max = +1.18 codes inl min = ?.06 codes 16384 lsb tpc 10. integral nonlinearity 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 40msps a in = 5mhz(?dbfs) snr = 72dbfs sfdr = 87.57dbc db tpc 11. single tone @ 5 mhz 0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?00 ?10 ?20 ?30 0 20.0 17.5 15.0 12.5 10.0 7.5 5.0 2.5 frequency ?mhz encode = 40msps a in = 18mhz(?dbfs) snr = 71.5dbfs sfdr = 78.7dbc db tpc 12. single tone @ 18 mhz
rev. a AD13465 C8C definition of specifications analog bandwidth the analog input frequency at which the spectral power of the fundamental frequency (as determined by the fft analysis) is reduced by 3 db. aperture delay th e delay between a differential crossing of encode and encode command and the instant at which the analog input is sampled. aperture uncertainty (jitter) the sample-to-sample variation in aperture delay. differential analog input resistance, differential analog input capacitance, and differential analog input impedance the real and complex impedances measured at each analog input port. the resistance is measured statically and the capaci- tance and differential input impedances are measured with a network analyzer. differential analog input voltage range the peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. peak differential voltage is computed by observing the voltage from the other pin, which is 180 degrees out of phase. peak-to-peak differential is computed by rotating the inputs phase 180 degrees and taking the peak measurement again. the difference is then computed between both peak measurements. differential nonlinearity the deviation of any code from an ideal 1 lsb step. encode pulsewidth/duty cycle pulsewidth high is the minimum amount of time that the encode pulse should be left in logic 1 state to achieve rated performance; pulsewidth low is the minimum time the encode pulse should be left in low state. at a given clock rate, these specs define an acceptable encode duty cycle. harmonic distortion the ratio of the rms signal amplitude to the rms value of the worst harmonic component. integral nonlinearity th e deviation of the transfer function from a reference line m easured in fractions of 1 lsb using a ?est straight line de termined by a least square curve fit. minimum conversion rate the encode rate at which the snr of the lowest analog signal frequency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the encode rate at which parametric testing is performed. output propagation delay th e delay between a differential crossing of encode and encode command and the time when all output data bits are within valid logic levels. overvoltage recovery time t he amount of time required for the converter to recover to 0.02% accuracy after an analog input signal of the specified percentage of full scale is reduced to midscale. power supply rejection ratio the ratio of a change in input offset voltage to a change in power supply voltage. signal-to-noise-and-distortion (sinad) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral components, including harmonics but excluding dc. may be reported in db (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). signal-to-noise ratio (without harmonics) the ratio of the rms signal amplitude (set at 1 db below full scale) to the rms value of the sum of all other spectral com ponents, excluding the first five harmonics and dc. may be reported in db (i.e., degrades as signal level is lowered) or in dbfs (always related back to converter full scale). spurious-free dynamic range the ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. the peak spurious component may or may not be a harmonic. transient response the time required for the converter to achieve 0.02% accuracy when a one-half full-scale step function is applied to the analog input. two-tone intermodulation distortion rejection the ratio of the rms value of either input tone to the rms value of the worst third order intermodulation product; reported in dbc. t a a in enc, enc d[13:0] dry n n+1 n+2 n+3 n+4 n n+1 n+2 n+3 n+4 n? n? n? n t encl t ench t enc t e_dr t od figure 1. timing diagram
rev. a AD13465 C9C amp-in-x-1 100 100 to ad8037 amp-in-x-2 figure 2. single-ended input stage loads loads encode 10k 10k encode av cc 10k 10k av cc av cc av cc figure 3. encode inputs current mirror current mirror dr out dv cc v ref dv cc figure 4. digital output stage current mirror current mirror d0?13 100 dv cc v ref dv cc figure 5. digital output stage theory of operation the AD13465 is a high dynamic range, 14-bit, 65 mhz pipeline delay (three pipelines) analog-to-digital converter. the custom analog input section provides input ranges of 1 v p-p and 2 v p-p, and input impedance configurations of 50 ? , 100 ? , and 200 ? . the AD13465 employs four monolithic adi components per channel (ad8037, ad8138, ad8031, and ad6644), along w ith multiple passive resistor networks and decoupling capacitors to fully integrate a complete 14-bit analog-to-digital converter. in t he single-ended input configuration, the input signal is passed t hrough a precision laser trimmed resistor divider allowing the user to externally select operation with a full-scale signal of 0.5 v or 1.0 v by choosing the proper input terminal for the applicati on. the result of the resistor divider is to apply a full-scale input ap proximately 0.4 v to the noninverting input of the internal ad8037 amplifier. the AD13465 analog input includes an ad8037 amplifier featuring an innovative architecture that maximizes the dynamic r ange capability on the amplifier? inputs and outputs. the ad8037 amp lifier provides a high input impedance and gain for driving the ad8138 in a single-ended-to-differential amplifier configuration. the ad8138 has a ? db bandwidth at 300 mhz and delivers a differential signal with the lowest harmonic distor tion av ailable in a differential amplifier. the ad8138 differential outputs help balance the differential inputs to the ad6644 maximizing the performance of the device. the ad8031 provides the buffer for the internal reference analog- to-digital converter. the internal reference voltage of the ad6644 is designed to track the offsets and drifts and is used to ensure matching over an extended temperature range of opera tion. the reference voltage is connected to the output common mode input on the ad8138. this reference voltage sets the output common mode on the ad8138 at 2.4 v, which is the midsupply level for the adc. the ad6644 has complementary analog input pins, ain and a in. each analog input is centered at 2.4 v and should swing 0.55 v around this reference. since ain and ain are 180 d egrees out of phase, the differential analog input signal is 2.2 v peak-to-peak. both analog inputs are buffered prior to the first track-and-hold. the ad6644 digital outputs drive 100 ? series resistors (figure 5). the result is a 14-bit parallel digital cmos compatible word, coded as two? complement. using the single-ended input the AD13465 has been designed with the user? ease of opera- tion in mind. multiple input configurations have been included on-board to allow the user a choice of input signal levels and input impedance. the standard inputs are 0.5 v and 1.0 v. the user can select the input impedance of the AD13465 on any input by using the other inputs as alternate locations for the gnd. the following chart summarizes the impedance options available at each input location. amp-in-x-1 = 100 ? when amp-in-x-2 is open. amp-in-x-1 = 50 ? when amp-in-x-2 is shorted to gnd. amp-in-x-2 = 200 ? when amp-in-x-1 is open. each channel has two analog inputs amp-in-a-1 and amp-in-a-2 or amp-in-b-1 and amp-in-b-2. use amp-in-a-1 or amp-in-b-1 when an input of 5 v full scale is desired. use
rev. a AD13465 C10C amp-in-a-2 or amp-in-b-2 when 1 v full scale is desired. each channel has an amp-out that must be tied to either a non- inverting or inverting input of a differential amplifier, with the remaining input grounded. for example, side a, amp-out-a (pin 6) must be tied to a+in (pin 5) with a?n (pin 4) tied to ground for noninverting operation or amp-out-a (pin 6) tied to a?n (pin 4) with a+in (pin 5) tied to ground for inverting operation. using the differential input each channel of the AD13465 was designed with two optional differential inputs, a+in, a?n and b+in, b?n. the inputs provide system designers with the ability to bypass the ad8037 amplifier and drive the ad8138 directly. the ad8138 differential adc driver can be deployed in either a single-ended or dif ferential input configuration. the differential analog inputs ha ve a nominal input impedance of 620 ? and nominal full- scale input range of 1.2 v p-p. the ad8138 amplifier drives a d iffer ential filter and the custom analog-to-digital converter. the d ifferential input configuration provides the lowest even-order harmonics and signal-to-noise (snr) performance improvement of up to 3 db (snr = 73 dbfs). exceptional care was ta ken in the layout of the differential input signal paths. the differential input transmission line characteristics are matched and bal anced. equal attention to system level signal paths must be provided in order to realize significant performance improvements. applying the AD13465 encoding the AD13465 the AD13465 encode signal must be a high quality, extremely low phase noise source to prevent degradation of performance. maintaining 14-bit accuracy at 65 msps places a premium on encode clock phase noise. snr performance can easily degrade 3 db to 4 db with 32 mhz input signals when using a high jitter clock source. see analog devices?application note an-501, aperture uncertainty and adc system performance , for complete details. for optimum performance, the AD13465 must be clocked differentially. the encode signal is usually ac-coupled into the encode and encode pins via a transformer or capacitors. these pins are biased internally and require no additional bias. shown below is one preferred method for clocking the AD13465. the clock source (low jitter) is converted from single-ended to differential using an rf transformer. the back-to-back schottky diodes across the transformer secondary limit clock excursions into the AD13465 to approximately 0.8 v p-p differential. this helps prevent the large voltage swings of the clock from feeding through to the other portions of the AD13465, and limits the noise presented to the encode inputs. a crystal clock oscillator can also be used to drive the rf transformer if an appropriate limited resistor (typically 100 ? ) is placed in the series with the primary. t1-4t 100 0.1mf encode encode AD13465 hsms2812 diodes clock source figure 6. crystal clock oscillatordifferential encode if a low jitter ecl/pecl clock is available, another option is to ac-couple a differential ecl/pecl signal to the encode input pins as shown below. a device that offers excellent jitter perfor- mance is the mc100lvel16 (or same family) from motorola. encode encode AD13465 0.1 f ecl/pecl vt vt 0.1 f figure 7. differential ecl for encode jitter consideration the signal-to-noise ratio (snr) for any adc can be predicted. when normalized to adc codes, the equation below, accurately predicts the snr based on three terms. these are jitter, average dnl error, and thermal noise. each of these terms contributes to the noise within the converter. snr f t v n analog rms noise rms n = + () ? ? ? ? ? ? ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? log ( ) 20 1 2 2 2 2 2 12 j f analog = analog input frequency t j rms = rms jitter of the encode (rms sum of encode source and internal encode circuitry) = average dnl of the adc (typically 0.50 lsb) n =n umber of bits in the adc v noise rms = the analog input of the adc (typically 5 lsb) for a 14-bit analog-to-digital converter like the AD13465, aper- ture jitter can greatly affect the snr performance as the analog frequency is increased. figure 8 shows a family of curves that demonstrates the expected snr performance of the AD13465 as jitter increases. the chart is derived from the above equation. for a complete discussion of aperture jitter, please consult analog devices?application note an-501, aperture uncertainty and adc system performance . clock jitter ?ps 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 snr ??bfs 60 61 62 63 64 65 66 67 68 69 70 71 59 58 4.0 4.4 4.8 5.0 a in = 5mhz a in = 32mhz a in = 21mhz a in = 9.9mhz figure 8. snr vs. jitter
rev. a AD13465 C11C power supplies ca re should be taken when selecting a power source. linear supplies are strongly recommended. switching supplies tend to have radiated components that may be received by the ad1 3465. each of the power supply pins should be decoupled as closely to the package as possible, using 0.1 f chip capacitors. t he AD13465 has separate digital and analog power supply pins. the analog supplies are denoted av cc and the digital supply pins are denoted dv cc . av cc and dv cc should be separate power supplies. this is because the fast digital output swings can couple switching current back into the analog supplies. note that av cc must be held within +5% and ?% of 5 v. the AD13465 is specified for dv cc = 3.3 v, since this is a common supply for digital asics. output loading care must be taken when designing the data receivers for the AD13465. the digital outputs drive an internal series resistor (e.g., 100 ? ) followed by a gate like 75lcx574. to minimize capacitive loading, there should be only one gate on each output pin. an example of this is shown in the evaluation board schematic shown in figure 10. the digital outputs of the AD13465 have a c onstant output slew rate of 1 v/ns. a typical cmos gate com bined with a pcb trace will have a load of approximately 10 pf. therefore, as each bit switches, 10 ma (10 pf 1 v 1 ns) of dynamic cur rent per bit will flow in or out of the device. a full-sc ale transition can cause up to 140 ma (14 bits 10 ma/bit) of transient current through the output stages. these switch ing currents are confined between ground and the dv cc pin. stan dard ttl gates should be avoided since they can appreciably add to the dynamic switching currents of the AD13465. it should also be noted that extra capacitive loading will increase output timing and invalidate timing specifications. digital output timing is guaran teed with 10 pf loads. figure 9. evaluation board mechanical layout evaluation board t he AD13465 evaluation board (figure 9) is designed to provide optimal performance for evaluation of the AD13465 analog-to-digital converter. the board encompasses everything needed to ensure the highest level of performance for evaluating th e AD13465. the board requires an analog input signal, encode clock, and power supply inputs. the clock is buffered on-board to p rovide clocks for the latches. the digital outputs and out clocks are available at the standard 40-pin connectors j1 and j2. power to the analog supply pins is connected via banana jacks. t he analog supply powers the associated components and the analog section of the AD13465. the digital outputs of the AD13465 are powered via banana jacks with 3.3 v. contact the factory if additional layout or applications assistance is required. layout information the schematics of the evaluation board (figures 10a?0c) repre- sent typical implementation of the AD13465. the pinout of the AD13465 is very straightforward and facilitates ease of use and the implementation of high frequency/high resolution design prac- tices. it is recommended that high quality ceramic chip capacitors be used to decouple each supply pin to ground directly at the device. all capacitors can be standard high quality ceramic chip capacitors. care should be taken when placing the digital output runs. because the digital outputs have such a high slew rate, the capacitive load- ing on the digital outputs should be minimized. circuit traces for the digital outputs should be kept short and connect directly to the receiving gate. internal circuitry buffers the outputs of the adc through a resistor network to eliminate the need to externally isolate the device from the receiving gate.
rev. a AD13465 C12C bill of materials list for evaluation board qty. component name ref/des value description manufacturing part number 2 74clx16373mtd u7, u8 latch 74lcx1673mtd (fairchild) 1 AD13465az u1 AD13465az AD13465az 2 adp3330 u5, u6 regulator adp3330art-3.3rl7 10 bjack bj1-bj10 banana jacks 108-0740-001 (johnson components) 2 bres0805 r41, r53 25 ? 0805 sm resistor efj-6geyj240v 4 bres0805 r38, r39, r55, r56 33 k ? 0805 sm resistor efj-6geyj333v 6 res2 r1, r2, r5, r7, r8, 50 ? 0805 sm resistor efj-6geyj333v r54 36 res2 r3, r4, r6, r9, 100 ? 0805 sm resistor efj-6geyj333v r12?15, r19?28, r31?36, r37, r42?46, r51, r52 28 cap2 c1, c2, c5?10, 0.1 f 0805 sm resistor grm 40x7r104k025bl c12, c16?18, c20?26, c28, c30?38 2 cap2 c13, c27 0.47 f 0805 sm resistor vj1206u474mfxmb 2 h40dm j1, j2 2 20 40-pin male connector tsw -120-08-g-d 6i nd2 l1?6 47 ? sm inductor 2743019447 4m c10el16 u2, u3, u9, u11 clock drivers mc1016ep16d 2m c100elt23 u4, u10 ecl/ttl clock drivers sy100elt23l 8 polcap2 c3, c4, c11, c14, 10 f tantalum polar caps t491c106m016a57280 c15, c19, c29, c30 4 res2 r47?50 0 ? 0805 sm resistor erj-6gey or 00v 12 sma j3?14 sma connectors 142-0701-201 4 stand-off stand-off 313-2477-016 ( johnson compo nents) 4 screws screws (stand-off) mpms 004 0005 ph (building fasteners) 1 pcb AD13465 eval board (rev b) gs03361
rev. a AD13465 C13C a gnda 10 a gnda 11 12 ?vaa 13 +5vaa 14 d2a 15 d3a 16 d4a 17 d5a 18 d6a 19 d7a 20 21 22 23 24 25 dgnda 26 a gndb 60 59 58 a gndb 57 56 55 54 53 encbb 52 encb 51 + 3.3vdb 50 d13b(msb) 49 d9b 48 d8b 47 d7b 46 d6b 45 dgndb 44 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 a gnda amp in a 2 a+in a?n a gnda shield a gndb a gndb d12a d13a(msba) shield drbout d3b d4b d5b dgndb u1 AD13465 d3a d4a d5a d6a d7a d2a dgnda a gnda a gnda encab d0a(lsb) d1a enca a gnda +3vda d0a d1a a gnda enca enca ?vaa c9 0.1 f c10 0.1 f c36 0.1 f out 3.3vda c34 0.1 f +5vaa a gnda a gnda c35 0.1 f a gnda amp in a 1 amp out a a gnda a gndb b?n b+in amp out b amp in b 1 amp in b 2 ?.2vab +5vab dgnda a gndb d10b d11b d12b d0b(lsbb) draout d11a d10a d9a d8a dgnda d12a d13a drbout d3b d4b d5b dgndb d0b draout d11a d10a d9a d8a dgnda e56 e55 lidb e65 e48 e40 dgnda dgndb e69 e70 e49 a gnda e51 e50 e72 e74 e77 e75 e73 e71 j4 sma a gnda j3 sma e76 e78 e83 e81 e79 a gnda j9 sma a gnda j13 sma a gnda e68 e66 a gndb e54 e53 j7 sma a gndb e86 e85 e52 a gndb a gndb j14 sma a gndb j8 sma a gndb j6 sma dgndb ?vab c33 0.1 f c18 0.1 f c37 0.1 f out 3.3vdb c17 0.1 f +5vab a gndb a gndb c38 0.1 f a gndb a gndb encb encb d13b d9b d8b d7b d6b dgndb a gndb d10b d11b d12b e67 lida e80 e82 e84 l1 c29 10 f +3vda u7 c62 0.1 f 47 20% @100mhz dgnda dut 3.3vda bj10 1 l2 c30 10 f +3vdb u8 c16 0.1 f 47 20% @100mhz dgndb dut 3.3vdb bj9 1 l3 c3 10 f +3vaa u1 c20 0.1 f 47 20% @100mhz a gnda +5vaa bj6 1 a gnda l4 c4 10 f +5vab u1 c21 0.1 f 47 20%@100mhz a gndb +5vab bj5 1 a gndb l5 c11 10 f ?vaa u1 c32 0.1 f 47 20%@100mhz a gnda ?vaa bj2 1 a gnda l6 c19 10 f ?vab u1 c31 0.1 f 47 20%@100mhz a gndb ?vab bj1 1 a gndb d1b d1b d2b d2b figure 10a. evaluation board
rev. a AD13465 C14C ( msb) b13b b12b b11b b10b b9b b8b f1b dgndb ( lsb) b0b b1b b2b b3b dgndb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 b7b b6b c14 10 f bu flatb r2 50 e64 e63 e62 draout 3.3vdb dgndb h40dn j2 f0b u7 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 41 42 r11, dni 25 26 27 28 113 112 vcc 111 110 gnd 19 18 17 16 gnd 15 13 12 gnd 11 10 14 vcc le2 115 114 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o3 o2 gnd o1 o0 o4 vcc oe2 o15 o14 gnd 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 24 23 22 21 dut 3.3vdb dgndb dgndb dgndb dut 3.3vdb dgndb dgndb r10, dni r30, dni r29, dni r28, 100 r27, 100 r26, 100 r12, 100 r9, 100 r35, 100 r34, 100 r33, 100 r32, 100 r31, 100 r25, 100 le1 oe1 dut 3.3vdb dgndb dgndb dgndb dut 3.3vdb dgndb r49 0 r50 0 dgndb r8 50 latchb e57 ( lsb) d0b d1b d4b d5b d6b d7b d8b d9b d10b d11b d12b ( msb) d13b f0b f1b b0b (lsb) b1b b2b b3b b4b b5b b6b b7b b8b b9b b10b b13b (msb) b11b b12b dgndb 74lcx16374 r36, 100 ( msb) b13a b12a b11a b10a b9a b8a f1a dgnda ( lsb) b0a b1a b2a b3a dgnda 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 b7a b6a c15 10 f bu flata r5 50 e61 e60 e59 draout 3.3vda dgnda h40dm j1 f0a u8 29 30 31 32 33 34 35 36 37 38 39 40 43 44 45 46 47 48 41 42 r18, dni 25 26 27 28 113 112 vcc 111 110 gnd 19 18 17 16 gnd 15 13 12 gnd 11 10 14 vcc le2 115 114 gnd o13 o12 vcc o11 o10 gnd o9 o8 o7 o6 gnd o5 o3 o2 gnd o1 o0 o4 vcc oe2 o15 o14 gnd 20 19 18 17 16 15 14 13 12 11 10 9 6 5 4 3 2 1 8 7 24 23 22 21 dut 3.3vda dgnda dgnda dgnda dut 3.3vda dgnda dgnda r17, dni r40, dni r44, dni r45, 100 r46, 100 r15, 100 r14, 100 r13, 100 r24, 100 r23, 100 r22, 100 r21, 100 r20, 100 r19, 100 r12, 100 le1 oe1 dut 3.3vda dgnda dgnda dgnda dut 3.3vda dgnda r47 0 r48 0 dgnda r7 50 latcha e58 ( lsb) d0a d1a d4a d5a d6a d7a d8a d9a d10a d11a d12a ( msb) d13a dgnda 74lcx16374 d2a d3a b4a b5a d2b d3b b4b b5b f0a f1a b0a (lsb) b1a b2a b3a b4a b5a b6a b7a b8a b9a b10a b13a (msb) b11a b12a figure 10b. evaluation board
rev. a AD13465 C15C nc = no connect vcc q vee nc d vbb u2 mc10el16 a gnda 1 2 3 4 8 7 6 5 out nr in sd u5 3 5 1 err gnd 4 adp3330 5 a gnda db qb c13 0.47 f 3.3va c7 0.1 f c8 0.1 f enca enca a gnda r42 100 r43 100 a gnda r56 33k nc = no connect vcc q vee nc d vbb u3 mc10el16 1 2 3 4 8 7 6 5 db qb nc = no connect vcc q0 vee nc d vbb u4 mc100ept23 1 2 3 4 8 7 6 5 db q1 3.3vda c6 0.47 f r55 33k dgnda c2 0.1 f r41 25 j12 sma j5 encode sma r1 50 c1 0.1 f a gnda a gnda a gnda dgnda dgnda a gnda r3 100 r4 100 dgnda dgnd c5 0.47 f + 3.3vda latcha bu flata e23 e19 +5vaa e17 e27 e25 e21 e32 e44 e42 e10 e33 e6 e18 e28 e26 e20 e31 e43 e41 e9 e34 e5 dgnda agnda e38 e29 e1 e36 e14 e37 e30 e2 e35 e13 dgndb agndb so1 so2 so3 so4 so5 so6 e45 e3 e46 e4 e15 e7 e16 e12 dgnda dgndb e11 e39 e8 e47 dgnda dgndb a gndb 1 bj3 a gnda 1 bj4 dgndb 1 bj7 dgndb dgnda 1 bj8 dgnda nc = no connect vcc q vee nc d vbb u11 mc10el16 a gndb 1 2 3 4 8 7 6 5 out nr in sd u6 3 5 1 err gnd 4 adp3330 5 a gndb db qb c27 0.47 f 3.3vb c24 0.1 f c28 0.1 f encb encb a gndb r52 100 r51 100 a gnda r38 33k nc = no connect vcc q vee nc d vbb u9 mc10el16 1 2 3 4 8 7 6 5 db qb nc = no connect vcc q0 vee nc d vbb u10 mc100ept23 1 2 3 4 8 7 6 5 db q1 3.3vdb c25 0.47 f r39 33k dgndb c23 0.1 f r53 25 j11 sma j10 encode sma r54 50 c22 0.1 f a gndb a gndb a gndb dgndb dgndb dgndb r37 100 r6 100 dgndb dgndb c26 0.1 f 3.3vda latchb bu flatb e24 e22 +5vab figure 10c. evaluation board
rev. a AD13465 C16C figure 11a. top silk figure 11b. top layer
rev. a AD13465 C17C figure 11c. gnd1 figure 11d. gnd2
rev. a AD13465 C18C figure 11e. bottom silk figure 11f. bottom layer
rev. a AD13465 C19C outline dimensions 68-lead ceramic leaded chip carrier with nonconductive tie-bar (es-68c) dimensions shown in inches and (millimeters) detail a 0.010 (0.254) 30 0.050 (1.27) 0.020 (0.508) 0.175 (4.45) max 0.235 (5.97) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) pin 1 top view (pins down) 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.040 (1.02) 45 0.015 (0.3) 45 3 pls 0.040 (1.02) r typ 0.350 (8.89) typ 2.000 (50.80) typ
rev. a C20C c01973C0C8/02(a) printed in u.s.a. AD13465 revision history location page 8/02?ata sheet changed from rev. 0 to rev. a. change to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 packages updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 outline dimensions 68-lead ceramic leaded chip carrier [clcc] (es-68c) dimensions shown in inches and (millimeters) toe down angle 0? degrees 0.010 (0.254) 30 0.050 (1.27) 0.020 (0.508) detail a rotated 90 ccw 1.190 (30.23) 1.180 (29.97) sq 1.170 (29.72) pin 1 10 26 9 61 60 43 27 44 top view (pins down) 0.800 (20.32) bsc 0.960 (24.38) 0.950 (24.13) sq 0.940 (23.88) 0.055 (1.40) 0.050 (1.27) 0.045 (1.14) 0.020 (0.508) 0.017 (0.432) 0.014 (0.356) 0.175 (4.45) max 0.235 (5.97) max detail a 0.010 (0.25) 0.008 (0.20) 0.007 (0.18) 0.060 (1.52) 0.050 (1.27) 0.040 (1.02) 1.070 (27.18) min

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